1. Field of the Invention
The present invention relates generally to a technique for protecting against electrostatic discharge damage during integrated circuit fabrication. More particularly, the present invention relates to a capacitor-triggered electrostatic discharge protection circuit.
2. Description of the Related Art
Electrostatic discharge, hereinafter "ESD", is a common phenomenon that occurs during handling of semiconductor integrated circuit ("IC") devices. An electrostatic charge may accumulate for various reasons and cause potentially destructive effects on an IC device. Damage typically can occur during a testing phase of an IC's fabrication, during assembly of the IC onto a circuit board, as well as during use of equipment into which the IC has been installed. Damage to a single IC due to poor ESD protection in an electronic device can partially or sometimes completely hamper its functionality. ESD protection for semiconductor ICs is, therefore, a reliability issue.
ESD stress models are based on the reproduction of typical discharge pulses to which the IC may be exposed during manufacturing or handling. Three standard models, known as the Human Body Model (HBM), Machine Model (MM), and Charged Device Model (CDM) have been developed. The human-body model is set forth in U. S. Military Standard MIL-STD-883, Method 3015.6. This Military Standard models the electrostatic stress produced on an IC device when a human carrying an electrostatic charge touches the lead pins of the IC device. The machine model is set forth in Industry Standard EIAJ-IC-121, which describes the electrostatic stress produced on an IC device when a machine carrying an electrostatic charge contacts the lead pins of the IC device. The charged device model describes the ESD current pulse generated when an IC device already carrying an electrostatic charge is grounded in the process of being handled.
Referring to FIGS. 1 and 2, circuit diagrams of ESD protection circuits conventionally used respectively with an input pad and an output pad of an IC package are schematically depicted. As shown in FIG. 1, an NMOS transistor M.sub.1 is utilized to protect an internal circuit 6 from the ESD stress that may appear at the input pad 5. The gate, source, and bulk of the NMOS transistor M.sub.1 are all tied to circuit ground V.sub.SS. The drain of the NMOS transistor M.sub.1 is connected to the input pad 5. As shown in FIG. 2, an output buffer consisting of an NMOS transistor M.sub.2 and a PMOS transistor M.sub.3 is employed to protect the internal circuit 6 from ESD damage at the output pad 7. Accordingly, gates of the NMOS and PMOS transistors are both coupled to the internal circuit 6, drains of which are tied together and to the output pad 7. Moreover, the source and bulk of the NMOS M.sub.2 are tied together and to circuit ground V.sub.SS. The source and bulk of the PMOS transistor M.sub.3 are tied together and to a V.sub.DD power rail. However, in light of the trend toward submicron scale IC fabrication, NMOS transistor vulnerability to ESD stress has been greatly reduced due to advanced processes, such as using lightly-doped drain (LDD) structure and clad silicide diffusions. Moreover, those devices with higher ESD immunity, such as a diode or a thick oxide device M.sub.4 shown in FIG. 3, have a triggering voltage higher than the breakdown voltage of a submicron-NMOS transistor. Accordingly, those devices are suited to operate in providing protection at the input pad 5, but are useless in providing protection at the output pad 7 because the ESD stress may cause damage to the NMOS transistor of an output buffer. In addition, the ESD pulse may damage the internal circuit 6 from the V.sub.DD to V.sub.SS power rail. As C. Duvvury et al. proposed in his paper "INTERNAL CHIP ESD PHENOMENA BEYOND THE PROTECTION CIRCUITS" in IEEE Transactions on Electron Devices, 35 (12), 1988, latchup effect degradation of circuit performance is unavoidable. Consequently, there is a need for an ESD protection circuit that can be used at any of the IC components likely to introduce ESD to the internal circuit, such as at an input pad, an output pad, or a power rail, in order to protect the internal circuit from ESD damage.